1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor integrated circuit capable of improving integration degree.
2. Description of the Related Art
In the following, a non-volatile memory will be described as an example which will not give any limitative sense to this invention.
It is always one target of a semiconductor integrated circuit to improve integration degree or density. This target is also applied to non-volatile memories such as EEPROM, flash EEPROM, and mask ROM.
FIGS. 5A and 5B are equivalent circuit diagrams of a NAND type flash EEPROM and a NOR type flash EEPROM. In the NAND circuit shown in FIG. 5A, a plurality of memory transistors T11, T21, . . . , T81 of eight bits are serially connected on the left side column, with the source and drain of adjacent transistors being connected in common. Select transistors SA1 and SB1 are connected to both ends of this column.
Similarly, on the right side column, memory transistors T12, T22, . . . , T82 of eight bits are serially connected, and select transistors SA2 and SB2 are connected to both ends of this column. Bit lines BL1 and BL2 are connected to ones of select transistors SA1 and SA2 at the external areas thereof, and each memory transistor has no bit contact.
The memory transistor has a stacked type gate electrode including a floating gate and a control gate, whereas the select transistor has a general single gate electrode. Eight word lines WL1, WL2, . . . , WL8 are connected to the control gates of first- to eighth-row memory transistors. Select lines SG1 and SG2 are connected to the gates of the select transistors.
Write/erase of each memory transistor is performed by draining/injecting electrons through tunneling. A read operation is performed by using serially connected eight memory transistors as one unit. Therefore, as compared to a NOR type, an access speed is lower. However, since the number of bit contacts is small, integration degree can be raised.
In the NOR type EEPROM shown in FIG. 5B, similar to the NAND type, although a plurality of transistors T11, T21, . . . are serially connected, the drains of memory transistors are connected to bit lines BL at every second bit and a source line SL is connected in common.
Data write is performed by applying a high electric field to the drain side and writing electrons into the floating gate through hot electron injection. Data erase is performed by draining electrons to the source line through tunneling.
In the NOR type EEPROM, each bit can be directly accessed so that an access time is short. However, since it is necessary to form one bit contact per two memory transistors, an occupied area becomes large and integration degree is inferior to the NAND type. Assuming the same cell capacity, it is generally said that the area of the NOR type is broader by about 20% than that of the NAND type.
If the threshold value of a channel region of a memory transistor is selectively changed and the stacked gate is changed to a single gate, a mask ROM can be formed. Similar to EEPROM, a NAND type and a NOR type of mask ROM can be formed.
A direct access to a transistor among a plurality of transistors requires a large substrate area and high integration is not easy.